The ability to conduct high-speed data communications between relatively remote data processing systems and associated subsystems is currently a principal requirement of a variety of industries and applications, such as business, educational, medical, financial and personal computer users. Moreover, it can be expected that present and future applications of such communications will continue to engender more such systems and services. One technology that has attracted particular interest in the telecommunication community is digital subscriber line (DSL) service. DSL technology enables a public switched telephone network (PSTN) to use existing telephone copper wiring infrastructure to deliver a relatively high data bandwidth digital communication service, that is selected in accordance with expected data transmission rate, the type and length of data transport medium, and schemes for encoding and decoding data.
FIG. 1 is a reduced complexity diagram of the general architecture of a DSL system, having a pair of mutually compatible digital communication transceivers 1 and 3 installed at remotely separated ‘west’ and ‘east’ sites 2 and 4, respectively, and coupled to a communication link 10, such as a twisted pair of an existing copper plant. One of these transceivers, for example, the west site transceiver 1, may be installed in a digital subscriber line access multiplexer (DSLAM) 6 of a network controller site (such as a telephone company central office (CO)). The DSLAM is coupled with an associated network backbone 5 that provides access to a number of information sources 7 and the Internet 8. As such, the west site transceiver 1 is used for the transport of digital communication signals, such as asynchronous transfer mode (ATM)-based packetized voice and data, from the west central office site 2 over the communication link 10 to an integrated access device (IAD) serving as the DSL transceiver 3 at the east end of the link, and may be coupled with a computer 9 at a customer premises, such as a home or office.
An integrated access device (IAD) is used to consolidate digitized data, voice and video traffic over a common wide area network (WAN) DSL link. The digitized voice stream may be digitally encoded as mu-law or a-law voice samples, such as supplied by an industry standard ITU G.711 codec, or it may comprise digitally encoded voice samples from an integrated services digital network (ISDN) phone. When these digitally encoded voice samples are encapsulated in accordance with packet or cell protocol for transport over the network (for example, using voice over asynchronous transfer mode (ATM) or voice over internet protocol (IP)), it is often desirable to incorporate into the IAD both echo cancellation and compression processing, in an effort to both optimize the signal quality and to maximize the bandwidth available for non-voice signaling. Commonly used industry standard signal processing operators for this purpose include ITU G.168 echo cancellation and ITU G.726 adaptive differential pulse code modulation (ADPCM) compression.
Now although these signal processing operators are available commercially as off-the-shelf components, they are usually based around a relatively costly digital signal processor (DSP) that occupies a substantial amount of circuit board real estate and consumes a large amount of power. However, the most undesirable attribute of such DSP-based operators is the fact that the downstream host processor, to which the data produced by the echo cancellation and compression engines of the DSP array is to be delivered, is burdened with the responsibility for performing data bus cycles in order to read the data.
This conventional architecture is diagrammatically shown in FIG. 2, wherein an array of dedicated DSPs 20 have their inputs derived from an incoming TDM stream 22, such as may be supplied by an array of codecs 24 which output digitized voice samples in accordance with voice signals supplied thereto from upstream POTS phones 26. The (compression and echo cancellation) processed data produced by the DSP array 20 is coupled over an associated parallel data bus structure 28 to a downstream host processor 25 for assembly into packets in accordance with an encapsulating protocol. The packets are then output over a digital communication link as a packetized voice output stream to a destination receiver device. Because the host processor must execute data bus cycles to read the digitized voice sample data produced by the DSP array, it suffers a relatively large performance burden which increases the latency of the system.